/projects/cubeos/src_current/hardware/mc68332.h Source File

00001 /*  src_experimental/hardware/mc68332.h
00002     CubeOS Version 0.4.90 experimental
00003     Copyright (C) 1999,2000 Holger Kenn
00004 
00005     CubeOS is free software; you can redistribute it and/or
00006     modify it under the terms of the GNU Library General Public
00007     License as published by the Free Software Foundation; either
00008     version 2 of the License, or any later version.
00009 
00010     CubeOS is distributed in the hope that it will be useful,
00011     but WITHOUT ANY WARRANTY; without even the implied warranty of
00012     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013     Library General Public License for more details.
00014 
00015 */  
00016 /* general cpu */
00017 
00018 #define SIM_MCR         SIM_BASE + 0x00 // Module Control register
00019 #define SIM_SYNCR       SIM_BASE + 0x04 // Clock synthesiser control register
00020 #define SIM_RSR         SIM_BASE + 0x07 // Reset Status
00021 #define SIM_SYPCR       SIM_BASE + 0x21 // System Protection
00022 #define SIM_PICR        SIM_BASE + 0x22 // Periodic Timer
00023 #define SIM_PITR        SIM_BASE + 0x24 //
00024 #define SIM_SWSR        SIM_BASE + 0x27 //
00025 #define SIM_CSPAR0      SIM_BASE + 0x44 // chip sellect pin assignment
00026 #define SIM_CSPAR1      SIM_BASE + 0x46 //
00027 #define SIM_CSBARBT     SIM_BASE + 0x48 // boot chip select
00028 #define SIM_CSORBT      SIM_BASE + 0x4a //
00029 #define SIM_CSBAR0      SIM_BASE + 0x4c // chip selects
00030 #define SIM_CSOR0       SIM_BASE + 0x4e
00031 #define SIM_CSBAR1      SIM_BASE + 0x50
00032 #define SIM_CSOR1       SIM_BASE + 0x52
00033 #define SIM_CSBAR2      SIM_BASE + 0x54
00034 #define SIM_CSOR2       SIM_BASE + 0x56
00035 #define SIM_CSBAR3      SIM_BASE + 0x58
00036 #define SIM_CSOR3       SIM_BASE + 0x5a
00037 #define SIM_CSBAR4      SIM_BASE + 0x5c
00038 #define SIM_CSOR4       SIM_BASE + 0x5e
00039 #define SIM_CSBAR5      SIM_BASE + 0x60
00040 #define SIM_CSOR5       SIM_BASE + 0x62
00041 #define SIM_CSBAR6      SIM_BASE + 0x64
00042 #define SIM_CSOR6       SIM_BASE + 0x66
00043 
00044 #define SIM_PEPAR       SIM_BASE + 0x17
00045 #define SIM_DDRE        SIM_BASE + 0x15
00046 #define SIM_PORTE       SIM_BASE + 0x11
00047 
00048 #define SIM_PFPAR       SIM_BASE + 0x1F
00049 #define SIM_DDRF        SIM_BASE + 0x1D
00050 #define SIM_PORTF       SIM_BASE + 0x19
00051 
00052 #define QSM_QSMCR       SCI_BASE + 0x00
00053 #define QSM_QTEST       SCI_BASE + 0x02
00054 #define QSM_QILR        SCI_BASE + 0x04
00055 #define QSM_QIVR        SCI_BASE + 0x05
00056 
00057 #define SCI_SCSR        SCI_BASE + 0x0c
00058 #define SCI_SCDR        SCI_BASE + 0x0e
00059 #define SCI_SCCR0       SCI_BASE + 0x08
00060 #define SCI_SCCR1       SCI_BASE + 0x0a
00061 
00062 #define SPI_SPCR0       SCI_BASE + 0x18
00063 #define SPI_SPCR1       SCI_BASE + 0x1a
00064 #define SPI_SPCR2       SCI_BASE + 0x1c
00065 #define SPI_SPCR3       SCI_BASE + 0x1e
00066 #define SPI_SPSR        SCI_BASE + 0x1f
00067 
00068 #define SPI_QPDR        SCI_BASE + 0x15
00069 #define SPI_QPAR        SCI_BASE + 0x16
00070 #define SPI_QDDR        SCI_BASE + 0x17
00071 
00072 #define QSM_PORTQS      SCI_BASE + 0x14
00073 #define QSM_PQSPAR      SCI_BASE + 0x16
00074 #define QSM_DDRQS       SCI_BASE + 0x17
00075 
00076 #define SPI_RDRAM               SCI_BASE + 0x100
00077 #define SPI_TDRAM               SCI_BASE + 0x120
00078 #define SPI_CMDRAM              SCI_BASE + 0x140
00079 
00080 #define CPURAMCTRL_MCR  CPURAMCTRL_BASE + 0x0
00081 #define CPURAMCTRL_TST  CPURAMCTRL_BASE + 0x2
00082 #define CPURAMCTRL_BAR  CPURAMCTRL_BASE + 0x4
00083 
00084