/projects/cubeos/src_current/drivers/tpu/tpud.c Source File

00001 /*  src_experimental/drivers/tpu/tpud.c
00002    CubeOS Version 0.4.90 experimental
00003    Copyright (C) 1999,2000 Holger Kenn
00004 
00005    CubeOS is free software; you can redistribute it and/or
00006    modify it under the terms of the GNU Library General Public
00007    License as published by the Free Software Foundation; either
00008    version 2 of the License, or any later version.
00009 
00010    CubeOS is distributed in the hope that it will be useful,
00011    but WITHOUT ANY WARRANTY; without even the implied warranty of
00012    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013    Library General Public License for more details.
00014 
00015  */
00016 #include <cubeos.h>
00017 #include <mc68681.h>            /* Probably not needed */
00018 #include <tpu.h>
00019 #include <tpud.h>
00020 #include <ivtab.h>
00021 
00022 #define WFSR 1000               
00023 
00024 /* \fn int TPU_init() 
00025    \ingroup TPU
00026    \brief prepares the TPU for first use.
00027 
00028    TPU_init() configures the global TPU registers. TPU_init() has to be invoked before
00029    using any other TPU function.
00030 
00031    The TPU consists of two 16-bit time bases (TCR1,TCR2) and 16 independent
00032    timer channels. A set of preprogrammed functions is coded in the micro
00033    engine. The host interface consists of the following genreal registers:
00034    - TPUMCR (Module Configuration)
00035    - STOP
00036    - TCR1P (2): Prescaler1 Divide
00037    - TCR2P (2): Prescaler2 Divide
00038    - EMU: Emulation Mode
00039    - T2CG: TCR2 Clock or Gate controlled
00040    - STF: Stop flag
00041    - SUPV: all registers supervisor controlled
00042    - PSCK: Prescaler Clock for TCR1
00043    - 00
00044    - IARB: Int. Arbitration Number
00045    - TICR (TPU Interrupt Configuration)
00046    - 00000
00047    - CIRL (3): Interrupt Request Level
00048    - CIBV (4): Interrupt Base Vector
00049    Each of the 15 channels is defined within a certain position in a set of
00050    registers. In a sequence of registers (e.g. R0,R1,R2,R3) the lower order 
00051    bits (in the register with the highest number) defines channel 0.
00052    The registers are:
00053    - CFSR: Channel Function Select
00054    - HSQR: Host Sequence (subfunction)
00055    - HSSR: Host Service Request (00 indicates host, that no service is being
00056    requested; a write signals the TPU a service request; the host
00057    should wait then until the request is processed; for a write all
00058    but the intended bits have to be 0!)
00059    - CPR:  Channel Priority (00=disabled,01=low,10=middle,11=high; it is
00060    recommended to perform an initialisation before setting an active
00061    priority)
00062    - CIER: Channel Interrupt Enable
00063    - CISR: Channel Interrupt Status (clear through read + write a 0)
00064    - CHPAR: Channel Parameter (6 for channels 0-13,8 for channels 14+15)
00065 
00066  */
00067 int TPU_init ()
00068 {
00069 
00070       setTPUMCR (0x4acd); //1Mhz/1Mhz setting
00071 //     0100  1010    1100 1101
00072 //     0 TCR1P:10 TCR2P:01 EMU:0 T2CG:1 STF:0
00073 //     SUPV:1 PSCK:1 IARB:1101 (13)
00074  
00075 //      setTPUMCR (0x0acd); // breaks TPU control loop for drive.c
00076 //     0000  1010    1100 1101
00077 //     0 TCR1P:00 TCR2P:01 EMU:0 T2CG:1 STF:0
00078 //     SUPV:1 PSCK:1 IARB:1101 (13)
00079 
00080 
00081 /*   STOP=0
00082    TCR1P=00 (divide by 1)
00083    TCR2P=01 (divide by 2)
00084    EMU=0
00085    T2CG=1 (T2CLK is enable for int. CLK/8 --> source for Prescaler2)
00086    SUPV=1
00087    PSCK=1 (int. CK/4 --> source for Prescaler1)
00088    IARB=d
00089 
00090    With 16 Mhz CLK:
00091    TCR1: 16 :4 :1 =4Mhz Clock
00092    TCR2: 16 :8 :2 =1Mhz Clock
00093 
00094  */
00095 
00096 
00097 /*      setTICR (((TPU_ILEVEL << 16) & 0x7) + TPU_VECTORBASE); */
00098 
00099         setTICR (0x480);
00100 
00101 /*   CIRL=4 TPU Interrupt Level
00102    CIBV=80  TPU Interrupt base
00103  */
00104 
00105         writeshort (TPU_CIER, 0);       /* Disable all interrupts */
00106 
00107         return (0);
00108 
00109 }
00110 
00111 
00116 int TPU_initchannel (unsigned char nr)
00117 {
00118         setCFSR (nr, 0);        /* 0 = off */
00119         setHSRR (nr, 0);        /* no host service request */
00120         setCIER (nr, 0);        /* no irq */
00121         setCPR (nr, 0);         /* and no priority */
00122         return (0);
00123 }
00124 
00125 /* \ingroup TPU
00126    \param TPU channel nr
00127    \brief makes TPU channel nr a direct digital input/output
00128  */
00129 int TPU_makedio (unsigned char nr)
00130 {
00131 
00132         setCFSR (nr, 8);        /* 9 = DIO */
00133         setHSRR (nr, 2);        /* Request Init */
00134         setCIER (nr, 0);        /* Interrupts disabled */
00135         setCPR (nr, 1);         /* Activate with low priority */
00136         return (0);
00137 }
00138 
00139 /* \ingroup TPU
00140    \brief sets the TPU channel nr to tristate or output level v
00141    \param TPU channel nr
00142    \param value v : v=0: low output v=1: high output v=255: tristate (input)
00143  */
00144 int TPU_setdio (unsigned char nr, unsigned char v)
00145 {
00146         if (nr > 15) {
00147                 return (-1);
00148         }
00149         if (getCFSR (nr) != 8) {
00150                 return (-1);
00151         }
00152         if (v == 255) {         /* input, means tri-state */
00153                 setHSQR (nr, 0);
00154                 setHSRR (nr, 3);
00155         } else {
00156                 if (v) {
00157                         setHSRR (nr, 1);
00158                 } else {
00159                         setHSRR (nr, 2);
00160                 }
00161         }
00162         return (0);
00163 }
00164 
00165 
00166 /* \ingroup TPU
00167    \brief reads logical state from TPU channel nr, returns -1 on failure
00168    0 or 1 as result on success
00169    \param TPU channel nr
00170  */
00171 int TPU_getdio (unsigned char nr)
00172 {
00173  if (nr > 15) {
00174   return (-1);
00175  }
00176  if (getCFSR (nr) != 8) {
00177   return (-1);
00178  }
00179  setHSQR (nr, 2);
00180  setHSRR (nr, 3);
00181  return ((getPAR(nr,1) & 0x8000)>0);
00182 }
00183 
00184 
00188 int TPU_makepwm_TCR1 (unsigned char nr)
00189 {
00190 
00191         setCFSR (nr, 9);        /* 9 = PWM */
00192         setPAR (nr, 0, 0x8c);   /* Time Base TCR1, toggle on match */
00193         setPAR (nr, 2, 0);      /* High Time */
00194         setPAR (nr, 3, 20875);  /* Period */
00195         setHSRR (nr, 2);        /* Request Init */
00196         setCIER (nr, 0);        /* Interrupts disabled */
00197         setCPR (nr, 2);         /* Activate with middle priority */
00198         return (0);
00199 
00200 }
00201 
00205 int TPU_makepwm_TCR2 (unsigned char nr)
00206 {
00207 
00208         setCFSR (nr, 9);        /* 9 = PWM */
00209         setPAR (nr, 0, 0xdc);   /* Time Base TCR2, toggle on match */
00210         setPAR (nr, 2, 0);      /* High Time */
00211         setPAR (nr, 3, 20875);  /* Period */
00212         setHSRR (nr, 2);        /* Request Init */
00213         setCIER (nr, 0);        /* Interrupts disabled */
00214         setCPR (nr, 2);         /* Activate with middle priority */
00215         return (0);
00216 
00217 }
00218 
00219 
00223 int TPU_makepwm (unsigned char nr)
00224 {
00225         return TPU_makepwm_TCR1 (nr);
00226 }
00227 
00233 int TPU_setpwmperiod (unsigned char nr, unsigned short period)
00234 {
00235         int i;
00236 
00237         if (nr > 15) {
00238                 return (-1);
00239         }
00240         if (getCFSR (nr) != 9) {
00241                 return (-1);
00242         }
00243         if (period>0x8000){
00244                 KERN_complain(4,"period for tp channel exceeds 0x8000");
00245                 return(-1);
00246         }
00247 
00248         i = 0;
00249         while ((getHSRR (nr) != 0) && (i < WFSR))
00250                 i++;
00251         if (i >= WFSR) {
00252                 return (-1);
00253         }
00254         setPAR (nr, 3, period); /* Par 3 = Period */
00255         setHSRR (nr, 1);        /* Immediate Update */
00256         return (0);
00257 }
00258 
00259 int TPU_setpwmdc (unsigned char nr, unsigned char hightime)
00260 {
00261         int i;
00262         unsigned long t;
00263 
00264         if (nr > 15) {
00265                 return (-1);
00266         }
00267         if (getCFSR (nr) != 9) {
00268                 return (-1);
00269         }
00270         if (hightime > 100) {
00271                 return (-1);
00272         }
00273         i = 0;
00274         while ((getHSRR (nr) != 0) && (i < WFSR))
00275                 i++;
00276         if (i >= WFSR) {
00277                 return (-1);
00278         }
00279         t = (getPAR (nr, 3) * hightime) / 100;  /* to avoid intermediate
00280                                                    overflow */
00281         setPAR (nr, 2, (unsigned short) t);     /* Par 2 = High Time */
00282         setHSRR (nr, 1);        /* Immediate Update */
00283         return (0);
00284 }
00285 int TPU_setpwmhigh (unsigned char nr, unsigned short hightime)
00286 {
00287         if (nr > 15) {
00288                 return (-1);
00289         }
00290         if (getCFSR (nr) != 9) {
00291                 return (-1);
00292         }
00293         setPAR (nr, 2, (unsigned short) hightime);
00294         /* Par 2 = High Time */
00295         return (0);
00296 }
00297 
00298 int TPU_makepac (unsigned char nr)
00299 {
00300         setCFSR (nr, 10);       /* 10 = ITC */
00301         setHSQR (nr, 1);        /* Continuous Mode, No links */
00302         setPAR (nr, 0, 0x4);    /* Input Channel, detect rising edge */
00303         setPAR (nr, 2, 0xffff); /* max count */
00304         setHSRR (nr, 1);        /* Request Init */
00305         setCIER (nr, 0);        /* Interrupts disabled */
00306         setCPR (nr, 2);         /* Activate with middle priority */
00307         return (0);
00308 
00309 }
00310 
00311 unsigned short TPU_getpac (unsigned char nr)
00312 {
00313         unsigned short v;
00314 
00315         if (nr > 15) {
00316                 return (0);
00317         }
00318         if (getCFSR (nr) != 10) {
00319                 return (0);
00320         }
00321         v = getPAR (nr, 3);     /* Read PAC */
00322         setHSRR (nr, 1);        /* Reset PAC */
00323         return (v);
00324 
00325 }
00326 
00327 
00328 
00329 
00330 int TPU_makeqd (unsigned char ch1, unsigned char ch2)
00331 {
00332 
00333         setCPR (ch1, 0);        /* Disable */
00334         setCPR (ch2, 0);
00335 
00336         setCFSR (ch1, TPU_FKT_QDEC);    /* Set QDEC */
00337         setCFSR (ch2, TPU_FKT_QDEC);
00338         setPAR (ch1, TPU_QDEC_CORR_PINSTATE_ADDR, ch2 * 16 + TPU_QDEC_CHAN_PINSTATE * 2);
00339         setPAR (ch2, TPU_QDEC_CORR_PINSTATE_ADDR, ch1 * 16 + TPU_QDEC_CHAN_PINSTATE * 2);
00340         setPAR (ch1, TPU_QDEC_EDGE_TIME_LSB_ADDR, ch2 * 16 + 1);
00341         setPAR (ch2, TPU_QDEC_EDGE_TIME_LSB_ADDR, ch2 * 16 + 1);
00342         setPAR (ch1, TPU_QDEC_POS_COUNT, 0x8000);
00343         setPAR (ch2, TPU_QDEC_POS_COUNT, 0x8000);       /* this is where the position 
00344 
00345                                                            goes */
00346         setHSQR (ch1, 0);
00347         setHSQR (ch2, 1);
00348         setHSRR (ch1, 3);
00349         setHSRR (ch2, 3);
00350         setCPR (ch1, 2);        /* Activate with middle priority */
00351         setCPR (ch2, 2);        /* Activate with middle priority */
00352         return (0);
00353 
00354 }
00355 
00356 short TPU_getqd (unsigned char nr)
00357 {
00358         short v;
00359 
00360         if (nr > 15) {
00361                 return (0);
00362         }
00363         if (getCFSR (nr) != TPU_FKT_QDEC) {
00364                 return (0);
00365         }
00366         v = getPAR (nr, TPU_QDEC_POS_COUNT);    /* Read PAC */
00367         setPAR (nr, TPU_QDEC_POS_COUNT, 0x8000);        /* Reset PAC */
00368         return (0x8000 - v);
00369 
00370 }
00371 
00372 short TPU_readqd (unsigned char nr)
00373 {
00374         short v;
00375 
00376         if (nr > 15) {
00377                 return (0);
00378         }
00379         if (getCFSR (nr) != TPU_FKT_QDEC) {
00380                 return (0);
00381         }
00382         v = getPAR (nr, TPU_QDEC_POS_COUNT);    /* Read PAC */
00383         return (0x8000 - v);
00384 
00385 }
00386 
00387 int TPU_setisr (unsigned char ch, void (*isr) (void))
00388 {
00389         return _KERN_IVTab_setvector (TPU_VECTORBASE + ch, isr);
00390 
00391 }
00392 
00393 int TPU_clearisr (unsigned char ch, void (*isr) (void))
00394 {
00395         return _KERN_IVTab_clearvector (TPU_VECTORBASE + ch, isr);
00396 
00397 }