An interupt request cycle is basically a read access to the device with the only difference, that the CPU uses no /CS and therefore the chip selects have to be decoded out of the address bus. Instead of a chip select the device looks for a signal with the same meaning on its /IACK port. Figure illustrates the access.
The differences in respect to the timing analysis only come only through a little later start of the access out of the view from the busmaster device. Because the /IACK has to be decoded out of the address bits, the activating edge of /IACK is a little later than an ordinary /CS would be. But this makes the setup conditions on that edge even more relexed and the hold time conditions have never been a problem. More precisely, we get
Consequently, the device will generate a later response to that starting edge, i.e.
The rest of the access is completely congruent to the read access.