The I2C bus driver and the DUART are mentioned to work with the MC68000 bus. Since the MC68332 has the same interface but is much faster, problems in the timing arise. In order to overcome these problems we embed the two components, i.e. we place a bidirectional driver into the data bus, which is controlled by a programmable logic device (GAL22V10). This device handles also the proper execution of the interupt acknowledge cycle.
Fig. shows the construction of the embedding. In the lower right part are the two I2Cbus controllers (PCF8584) and the DUART (SCN68681). The GAL reads the bus control signals and controls the data bus driver (ABT652). In addition, it interfaces the data acknowledge signal to the CPU (/DACKO). In the upper part of the figure is a block for fast binary output depicted. With help of an address comparator (ALS518) the GAL decodes the write access to the register (ABT16823) and generates its clock. Eight of the outputs serve as direction control for two dual motor controls. The other eight outputs are unbound and can serve as fast binary outputs.
In the first section, we describe the control equations of the GAL for both blocks. In section two, we deal with the embedding of the two kinds of busmaster chips. Then, in the third section we show the details of the implementation of the binary output block.